Advanced VLSI Design and Verification Course  VLSI-RN
 



Category:      Full Time course
 
Duration:       Six Months  [4 months Training and 2 months Internship]
 
Timings:        09 AM to 6 PM 
 
Eligibility:     BE/BTech in EEE/ECE/TE/CSE/IT/Instrumenation
                     ME/MTech/MS in Electronics/MSc Electronics


 

Key Features of VLSI-RN
 
  • ASIC & FPGA design methodologies 
  • Training and Internship
  • Advanced Logic Design     
  • FPGA Architecture
  • ASIC Verification Methodologies
  • HVL: SystemVerilog
  • HDL: Verilog 
  • Assertion Based Verification: SVA
  • UVM
  • Three Mini Projects
  • Industry Standard Project 
  • Scripting Language : Perl 
  • Operating System - Linux  
  • EDA Tools: Mentor Graphics - Questa, Modelsim SE and DE
  • Xilinx - ISE

Industry Standard Live Projects

[ Sample Projects List for Reference ]
  • AHB2APB Bridge RTL
  • PCS Subsystem RTL design
  • SPI IP core RTL design
  • UART IP core RTL Design
  • AHB UVC - Master agent in UVM
  • AHB2APB Bridge verification in UVM
  • UART IP Verification in UVM
  • AHB UVC - Slave agent in UVM
  • GPIO Verification in UVM
  • PCS subsystem IP Verification - UVM
  • AXI UVC- Master agent in UVM
  • I2C Real Time Clock IP design
  • ICPIT Verification in UVM
  • AXI UVC - Slave agent in UVM
  • SPI IP verification - UVM

Please reach us directly at,
Mobile:  +91 99012 78009


VLSI-RN Brochure